
A guide to applying software design principles and coding practices to VHDL to improve the readability, maintainability, and quality of VHDL code. This book addresses an often-neglected aspect of the creation of VHDL designs. A VHDL description is also source code, and VHDL designers can use the best practices of software development to write high-quality code and to organize it in a design. This book presents this unique set of skills, teaching VHDL designers of all experience levels how to apply the best design principles and coding practices from the software world to the world of hardware. The concepts introduced here will help readers write code that is easier to understand and more likely to be correct, with improved readability, maintainability, and overall quality. After a brief review of VHDL, the book presents fundamental design principles for writing code, discussing such topics as design, quality, architecture, modularity, abstraction, and hierarchy. Building on these concepts, the book then introduces and provides recommendations for each basic element of VHDL code, including statements, design units, types, data objects, and subprograms. The book covers naming data objects and functions, commenting the source code, and visually presenting the code on the screen. All recommendations are supported by detailed rationales. Finally, the book explores two uses of VHDL: synthesis and testbenches. It examines the key characteristics of code intended for synthesis (distinguishing it from code meant for simulation) and then demonstrates the design and implementation of testbenches with a series of examples that verify different kinds of models, including combinational, sequential, and FSM code. Examples from the book are also available on a companion website, enabling the reader to experiment with the complete source code.
| Dimensions | 18.6 x 3.2 x 23.6 cm |
| Isbn 10 | 0262034220 |
| Isbn 13 | 978-0262034227 |
| Item Weight | 1 kg 10 g |
| Language | English |
| Print Length | 624 pages |
| Publication Date | 27 May 2016 |
| Publisher | The MIT Press |
| Reading Age | 18 years and up |
User
Il migliore per il VHDL
La bibbia del VHDL moderno. Un ottimo libro per imparare il VHDL e per avere una referenza per ogni dubbio. L'autore copre anche feature del VHDL-2008 portando un po di modernità in questo vecchio linguaggio. Unica possibile addizione sarebbe quella di progetti avanzati in VHDL come microprocessori
User
Outstanding resource
I've taught both software and logic design courses. In the software world, coding style is a central part of the curriculum and grading policy - more than getting the answer right, it's about getting the answer well. I see that far less in the VHDL/Verilog world, at least in academia. That leaves students poorly prepared for industrial logic design practice and for design efforts much larger than a homework assignment. This book fills a sorely felt need.I recommend this to two audiences. Many of the concepts and practices in this book lie beyond what a beginning student could grasp; it's not for someone struggling with notions of clocked logic and state machines. I do recommend it, however, to advanced students and to industrial logic designers struggling with multi-person projects, re-usability, engineers fresh out of school, and other issues of scale. Although individual design elements might be (and often should be) small, problematic practices at the lower levels propagate and interact as components are assembled into larger structures. The best time to weed them out is the earliest time. Second, I recommend this to anyone teaching introductory courses. They're positioned to introduce good style, legibility, and safe design practices from the first assignments on, just as in the software world. Even if many of the practices recommended here will be familiar - and they will to anyone who's seen similar guides for software design - seeing them gathered and organized into a coherent body of practice can be very helpful. Some practices will seem excessive for small projects, and instructors will choose what matters at each level. Still, it will be helpful to give students, especially in the higher levels, some idea of what they'll be expected to know once they leave school.It's hard to find fault with these recommendations. I did find a few points of emphasis where opinions might differ, however. Real-world logic design commonly uses component libraries, including things like RAMs, FIFOs, arithmetic elements, transceivers, PLLs, and lots of other elements hardened into FPGA fabric or ASIC design flows. Also, tools for specific logic fabrics generally include idiosyncratic (and non-portable) pragmas for guiding synthesis. Wherever possible, designers should draw on such technology-specific utilities instead of rolling their own. If portability across technologies or tool flows becomes an issue, good modular design can help isolate such technology specifics and make them easy to swap out. Jasinski also discusses synthesizable vs non-synthesizable constructs, a concept I find very important. My own preference, in the interest of clarity, is to emphasize the distinction early on, and to keep non-synthesizable constructs out of 'payload' logic entirely. Of course, this brings up the gray area of compile-time constant expressions. This text mentions them briefly, though not by that name, but I feel that they deserve a longer, more rigorous discussion that demonstrates creative ways they can be used. Perhaps integer division or a floating-point sine function can not be synthesized directly. Still, designers can safely use such functions to generate fixed-point constants that can be synthesized.This could pair well with its kin from the software world. Although they'd overlap in many areas, software design guides offer suggestions not mentioned here. For example, this book points out that VHDL supports operator and function overloading. I did not see mentions of the hazards of overloading, however. A two-parameter function can do whatever your imagination can dream up. But, if you overload the binary '+' operator with any function other than addition of some kind, or if you endow it with wild side effects, you're well on your way to unmaintainable and unusable code, no matter what language it's in. Minor points aside, I recommend this highly to architects developing style guides and to educators (including self-educators) at every level.-- wiredweird
User
Five stars
Excellent book!
User
Glad I bought it
Reall good book, probably my favour one on this subject so far
User
A Professional Imprint to the Language
The best book to add a professional imprint to the knowledge of the language. Every chapter is packed of useful advices and comparisons to guide the designers‘s decisions of approaching problems with the language. I really appreciated the chapter on testing, very detailed on different techniques to test different kind of design (combinatorial, sequential, FSM and so on). I don’t recall similar books, therefore I warmly suggest it if you want to improve the quality of your designs.
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